1. Field of the Invention
The present invention relates to a socket and an adapter for an integrated circuit which permit an integrated circuit such as a CPU package to be mounted on a primary wiring board such as a motherboard, and to an integrated circuit assembly, such as a CPU accelerator, which utilizes the socket and the adapter.
2. Description of Related Art
Motherboards incorporated in personal computers are generally provided with a socket for mounting of a CPU. The socket is adapted to be fitted with a so-called PGA (pin grid array) package containing a chip such as a CPU.
With rapid CPU development, higher performance CPUs have successively be introduced onto the market. Personal computers are upgraded for higher-speed computation by replacing a CPU of old type with a higher-performance CPU of new type. The upgrade is indispensable for using more advanced software without any stress while efficiently utilizing existing hardware resources.
However, the old CPU and the new CPU do not necessarily have the same driving voltage and the same signal pin array, so that the upgrade cannot be achieved as desired only by the replacement of the PGA package.
The upgrade of the CPU is typically achieved by employing an adapter for adaptation of the driving voltage and signals between the socket on the motherboard of the existing personal computer and the new CPU. The most common product for the CPU upgrade on the market is a CPU accelerator which includes an adapter as described above and a CPU of new type in combination.
FIG. 11 is a schematic diagram illustrating the construction of a conventional CPU accelerator. In FIG. 11, the CPU accelerator 100 attached to a socket 121 of a motherboard 120 is viewed along a surface of the motherboard 120. The socket 121 is a so-called "Socket7" which is mounted on the motherboard 120. A PGA package 130 (CPU package) incorporating a CPU is usually attached to the socket 121 as shown in FIG. 13.
Referring to FIG. 11, the CPU accelerator 100 includes a PGA package 101 (CPU package) incorporating a CPU, a PGA socket 102 fitted with the PGA package 101, a first intermediate printed wiring board 103 having the PGA socket 102 mounted thereon, a second intermediate printed wiring board 104 for adaptation of a driving voltage, a signal and the like, and a cooling device 105 provided on the PGA package 102 for cooling the CPU.
The PGA socket 102 receives and holds all of a plurality of pins 106 projecting from a lower surface of the PGA package 101. More specifically, a plurality of pins 107 are implanted in a lower surface of the PGA socket 102, and respectively have pin holders provided at heads thereof for receiving and holding the pins 106 of the PGA package 101. The pins 107 of the PGA socket 102 are all fixed onto the first intermediate printed wiring board 103 by soldering.
The first intermediate printed wiring board 103 is provided with a voltage regulator circuit for transforming a voltage supplied from the motherboard 120, for example, from 3.3V to 2.2V and supplying the voltage to the PGA package 101, a circuit for setting a clock factor for generating a CPU drive clock by multiplying a base clock supplied from the motherboard 120 by an integer, a power supply circuit for supplying power to the cooling fan 105, and the like.
The plurality of pins 107 of the PGA socket 102 include signal pins 107A for transmission of an address signal and a data signal, setting pins 107B for transmission of a clock factor setting signal and the like, and relay pins 107C for supplying a source voltage from the first intermediate printed wiring board 103 to the PGA package 101 and for transmitting a signal which needs to be subjected to a signal adaptation process.
A plurality of pins 111 project from a lower surface of the first intermediate printed wiring board 103 in a parallel relation. Of the plurality of pins 111, pins 111A which are implanted in association with the signal pins 107A are respectively connected to the signal pins 107 via solder portions 112 embedded in through-holes formed in the first intermediate printed wiring board 103 as shown in FIG. 12 on a greater scale. The pins 111 are provided neither in association with the setting pins 107B nor just below the relay pins 107C. The relay pins 107C are each connected to the voltage regulator circuit or the like on the first intermediate printed wiring board 103 or to an interconnection conductor provided on the first intermediate printed wiring board 103. Of the plurality of pins 111, pins 111C associated with the relay pins 107C are implanted in positions not just below the relay pins 107C.
A circuit for supplying a source voltage from the motherboard to the pins 111C and a circuit for converting a pin arrangement are provided on the second intermediate printed wiring board 104. The pins 111A of the first intermediate printed wiring board 103 associated with the signal pins 107A extend through the second intermediate printed wiring board 104 to be held thereby. Further, the second intermediate printed wiring board 104 has pins 113 associated with the pins 111C in a coaxial relation with respect to the relay pins 107C. The pins 113 and the pins 111A are fitted in the socket 121 on the motherboard 120.
With the CPU accelerator 100 being mounted on the motherboard 120 as shown in FIG. 11, a lower surface of the second intermediate printed wiring board 104 abuts against an upper surface of the socket 121, whereby the pins 113, 111A are prevented from being inserted slantwise into the socket 121.
In the conventional CPU accelerator 100 described above, however, the two intermediate printed wiring boards, i.e., the first and second intermediate printed wiring boards 103 and 104, are vertically stacked, so that a great number of components are incorporated therein. This increases component costs and production costs with an increased number of assembly steps.
With the two printed wiring boards vertically stacked, the CPU accelerator 100 inevitably has a greater height. Particularly, where the CPU accelerator 100 is to be accommodated in a smaller-size housing, the CPU accelerator will suffer from limitations of space, thereby spatially interfering with other components or interior wall surfaces of the housing.